1. Field of the Invention
The invention relates to simulation and testing of integrated circuit performance, and more particularly to segment scan simulation of integrated circuit element performance.
2. Background Art
In the design of a large scale microprocessor, with many issues of complex architectural design, circuit design, CAD design, and photomask design, a successful functional scan verification of the many elements of the microprocessor becomes critical to the successful reduction of these elements to a Release Instruction Tape (“RIT”). One way of accomplishing design and fabrication verification is through the use of a scan ring. A scan ring, designed into the microprocessor, is a chain of serially connected latches. In this context, the chain or chains of serially connected latches are used for initialization and/or debugging of the microprocessor.
However, if the scan ring is defective or broken, basic access to the device is limited and quick accurate diagnosability becomes a severe problem. Therefore, the scannability of the scan ring is often simulated and verified before the design is reduced to a Release Instruction Tape. The scannability of the scan ring is deemed verified if the scan ring is shifted once completely around the scan ring and each latch on the ring retains its initial scan data at the end of shifting.
If the full scan ring fails to rotate (shift) successfully, there are several methods used traditionally to detect and diagnose the specific broken area of the scan ring. However, these methods are not only time consuming, but they may fail to detect the broken ring during simulation.
Thus, a clear need exists for an improved apparatus and method for diagnosing the broken functional rings of the microprocessor.